Information

Timer n
Timer 1
PIT
Registers
Peripheral
load_value
PIT
Triggers
Bus Clock
Bus
Peripheral
Iinterrupts
Figure 38-1. Block diagram of the PIT
NOTE
Refer to the Chip Configuration information for the number of
PIT channels used in this MCU.
38.1.2 Features
The main features of this block are:
• Timers can generate DMA trigger pulses
• Timers can generate interrupts
• All interrupts are maskable
• Independent timeout periods for each timer
38.2 Signal Description
The PIT module has no external pins.
Signal Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1014 Freescale Semiconductor, Inc.