Information

38.3 Memory Map/Register Description
This section provides a detailed description of all registers accessible in the PIT module.
NOTE
Reserved registers will read as 0, writes will have no effect.
NOTE
Refer to the Chip Configuration information for the number of
PIT channels used in this MCU.
PIT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_7000 PIT Module Control Register (PIT_MCR) 32 R/W 0000_0002h
38.3.1/
1016
4003_7100 Timer Load Value Register (PIT_LDVAL0) 32 R/W 0000_0000h
38.3.2/
1017
4003_7104 Current Timer Value Register (PIT_CVAL0) 32 R/W 0000_0000h
38.3.3/
1017
4003_7108 Timer Control Register (PIT_TCTRL0) 32 R/W 0000_0000h
38.3.4/
1018
4003_710C Timer Flag Register (PIT_TFLG0) 32 R/W 0000_0000h
38.3.5/
1018
4003_7110 Timer Load Value Register (PIT_LDVAL1) 32 R/W 0000_0000h
38.3.2/
1017
4003_7114 Current Timer Value Register (PIT_CVAL1) 32 R/W 0000_0000h
38.3.3/
1017
4003_7118 Timer Control Register (PIT_TCTRL1) 32 R/W 0000_0000h
38.3.4/
1018
4003_711C Timer Flag Register (PIT_TFLG1) 32 R/W 0000_0000h
38.3.5/
1018
4003_7120 Timer Load Value Register (PIT_LDVAL2) 32 R/W 0000_0000h
38.3.2/
1017
4003_7124 Current Timer Value Register (PIT_CVAL2) 32 R/W 0000_0000h
38.3.3/
1017
4003_7128 Timer Control Register (PIT_TCTRL2) 32 R/W 0000_0000h
38.3.4/
1018
4003_712C Timer Flag Register (PIT_TFLG2) 32 R/W 0000_0000h
38.3.5/
1018
Table continues on the next page...
Chapter 38 Periodic Interrupt Timer (PIT)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1015