Information

NOTE
Burst-access cannot occur across the 0x2000_0000 boundary
that separates the two SRAM arrays. The two arrays should be
treated as separate memory ranges for burst accesses.
3.5.3.5 SRAM arbitration and priority control
The MCM's SRAMAP register controls the arbitration and priority schemes for the two
SRAM arrays.
3.5.4 SRAM Controller Configuration
This section summarizes how the module has been configured in the chip.
Cortex-M4
core
MPU
Crossbar
switch
SRAM controller
Transfers
SRAM
upper
SRAM
lower
MPU
Figure 3-27. SRAM controller configuration
Table 3-38. Reference links to related information
Topic Related module Reference
System memory map System memory map
Power management Power management
Power management
controller (PMC)
PMC
Transfers SRAM SRAM
ARM Cortex-M4 core ARM Cortex-M4 core
MPU Memory protection unit
Configuration MCM MCM
3.5.5 System Register File Configuration
This section summarizes how the module has been configured in the chip.
Memories and Memory Interfaces
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
102 Freescale Semiconductor, Inc.