Information

39.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)
Addresses: LPTMR0_CSR is 4004_0000h base + 0h offset = 4004_0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 TCF
TIE TPS TPP TFC
TMS
TEN
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPTMRx_CSR field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
TCF
Timer Compare Flag
The timer compare flag is set when the LPTMR is enabled and the LPTMR Counter Register equals the
LPTMR Compare Register and increments. This Timer Compare Flag is cleared when the LPTMR is
disabled or a logic one is written to the Timer Compare Flag.
0 LPTMR Counter Register has not equaled the LPTMR Compare Register and incremented
1 LPTMR Counter Register has equaled the LPTMR Compare Register and incremented
6
TIE
Timer Interrupt Enable
When the Timer Interrupt Enable is set, the LPTMR Interrupt is generated whenever the Timer Compare
Flag is also set.
0 Timer Interrupt Disabled.
1 Timer Interrupt Enabled.
5–4
TPS
Timer Pin Select
The Timer Pin Select configures the input source to be used in Pulse Counter mode. The Timer Pin
Select should only be altered when the LPTMR is disabled. The input connections vary by device. See the
Chip Configuration details for information on the connections to these inputs.
00 Pulse counter input 0 is selected.
01 Pulse counter input 1 is selected.
10 Pulse counter input 2 is selected.
11 Pulse counter input 3 is selected.
3
TPP
Timer Pin Polarity
Table continues on the next page...
Memory map and register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1026 Freescale Semiconductor, Inc.