Information

40.6.3 CMT Carrier Generator High Data Register 2 (CMT_CGH2)
This data register contain the secondary high value for generating the carrier output.
Address: CMT_CGH2 is 4006_2000h base + 2h offset = 4006_2002h
Bit 7 6 5 4 3 2 1 0
Read
SH
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CGH2 field descriptions
Field Description
7–0
SH
Secondary Carrier High Time Data Value
When selected, these bits contain the number of input clocks required to generate the carrier high time
period. When operating in Time mode, this register is never selected. When operating in FSK mode, this
register and the primary register pair are alternately selected under control of the modulator. The
secondary carrier high time value is undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
40.6.4 CMT Carrier Generator Low Data Register 2 (CMT_CGL2)
This data register contain the secondary low value for generating the carrier output.
Address: CMT_CGL2 is 4006_2000h base + 3h offset = 4006_2003h
Bit 7 6 5 4 3 2 1 0
Read
SL
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CGL2 field descriptions
Field Description
7–0
SL
Secondary Carrier Low Time Data Value
When selected, these bits contain the number of input clocks required to generate the carrier low time
period. When operating in Time mode, this register is never selected. When operating in FSK mode, this
register and the primary register pair are alternately selected under control of the modulator. The
secondary carrier low time value is undefined out of reset. These bits must be written to nonzero values
before the carrier generator is enabled when operating in FSK mode.
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1042 Freescale Semiconductor, Inc.