Information

CMT_CMD1 field descriptions
Field Description
7–0
MB[15:8]
These bits control the upper mark periods of the modulator for all modes.
40.6.8 CMT Modulator Data Register Mark Low (CMT_CMD2)
The contents of this register are transferred to the modulator down counter upon the
completion of a modulation period.
Address: CMT_CMD2 is 4006_2000h base + 7h offset = 4006_2007h
Bit 7 6 5 4 3 2 1 0
Read
MB[7:0]
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
CMT_CMD2 field descriptions
Field Description
7–0
MB[7:0]
These bits control the lower mark periods of the modulator for all modes.
40.6.9 CMT Modulator Data Register Space High (CMT_CMD3)
The contents of this register are transferred to the space period register upon the
completion of a modulation period.
Address: CMT_CMD3 is 4006_2000h base + 8h offset = 4006_2008h
Bit 7 6 5 4 3 2 1 0
Read
SB[15:8]
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1046 Freescale Semiconductor, Inc.