Information

RTC_WAR field descriptions (continued)
Field Description
1
TPRW
Time Prescaler Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the time prescaler register are ignored.
1 Writes to the time prescaler register complete as normal.
0
TSRW
Time Seconds Register Write
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Writes to the time seconds register are ignored.
1 Writes to the time seconds register complete as normal.
41.2.10 RTC Read Access Register (RTC_RAR)
Address: RTC_RAR is 4003_D000h base + 804h offset = 4003_D804h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
IERR
LRR
SRR
CRR
TCRR
TARR TPRR TSRR
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
RTC_RAR field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
IERR
Interrupt Enable Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the interrupt enable register are ignored.
1 Reads to the interrupt enable register complete as normal.
6
LRR
Lock Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the lock register are ignored.
1 Reads to the lock register complete as normal.
5
SRR
Status Register Read
Once cleared, this bit is only set by system reset. It is not affected by VBAT POR or software reset.
0 Reads to the status register are ignored.
1 Reads to the status register complete as normal.
Table continues on the next page...
Register definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1070 Freescale Semiconductor, Inc.