Information

This low power mode is entered when Stop Mode is requested at MCU level and the
LPM_ACK bit in the MCR Register is asserted by the FlexCAN. When in Stop
Mode, the module puts itself in an inactive state and then informs the CPU that the
clocks can be shut down globally. Exit from this mode happens when the Stop Mode
request is removed or when activity is detected on the CAN bus and the Self Wake
Up mechanism is enabled. See Stop Mode for more information.
42.2 FlexCAN Signal Descriptions
The FlexCAN module has two I/O signals connected to the external MCU pins. These
signals are summarized in the following table and described in more detail in the next
sub-sections.
Table 42-1. FlexCAN Signal Descriptions
Signal Description I/O
CAN Rx CAN Receive Pin Input
CAN Tx CAN Transmit Pin Output
42.2.1 CAN Rx
This pin is the receive pin from the CAN bus transceiver. Dominant state is represented
by logic level '0'. Recessive state is represented by logic level '1'.
42.2.2 CAN Tx
This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by
logic level '0'. Recessive state is represented by logic level '1'.
42.3 Memory Map/Register Definition
This section describes the registers and data structures in the FlexCAN module. The base
address of the module depends on the particular memory map of the MCU.
42.3.1 FlexCAN Memory Mapping
FlexCAN Signal Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1082 Freescale Semiconductor, Inc.