Information

The FlexCAN module can store CAN messages for transmission and reception using
Mailboxes and Rx FIFO structures.
This module's memory map includes sixteen 128-bit message buffers (MBs) that occupy
the range from offset 0x80 to 0x17F.
CAN memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_4000 Module Configuration Register (CAN0_MCR) 32 R/W D890_000Fh
42.3.2/
1088
4002_4004 Control 1 Register (CAN0_CTRL1) 32 R/W 0000_0000h
42.3.3/
1093
4002_4008 Free Running Timer (CAN0_TIMER) 32 R/W 0000_0000h
42.3.4/
1096
4002_4010 Rx Mailboxes Global Mask Register (CAN0_RXMGMASK) 32 R/W
FFFF_
FFFFh
42.3.5/
1097
4002_4014 Rx 14 Mask Register (CAN0_RX14MASK) 32 R/W
FFFF_
FFFFh
42.3.6/
1098
4002_4018 Rx 15 Mask Register (CAN0_RX15MASK) 32 R/W
FFFF_
FFFFh
42.3.7/
1099
4002_401C Error Counter (CAN0_ECR) 32 R/W 0000_0000h
42.3.8/
1100
4002_4020 Error and Status 1 Register (CAN0_ESR1) 32 R/W 0000_0000h
42.3.9/
1101
4002_4024 Interrupt Masks 2 Register (CAN0_IMASK2) 32 R/W 0000_0000h
42.3.10/
1105
4002_4028 Interrupt Masks 1 Register (CAN0_IMASK1) 32 R/W 0000_0000h
42.3.11/
1106
4002_402C Interrupt Flags 2 Register (CAN0_IFLAG2) 32 R/W 0000_0000h
42.3.12/
1106
4002_4030 Interrupt Flags 1 Register (CAN0_IFLAG1) 32 R/W 0000_0000h
42.3.13/
1107
4002_4034 Control 2 Register (CAN0_CTRL2) 32 R/W 00C0_0000h
42.3.14/
1110
4002_4038 Error and Status 2 Register (CAN0_ESR2) 32 R/W 0000_0000h
42.3.15/
1113
4002_4044 CRC Register (CAN0_CRCR) 32 R 0000_0000h
42.3.16/
1114
4002_4048 Rx FIFO Global Mask Register (CAN0_RXFGMASK) 32 R/W
FFFF_
FFFFh
42.3.17/
1115
4002_404C Rx FIFO Information Register (CAN0_RXFIR) 32 R Undefined
42.3.18/
1116
Table continues on the next page...
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1084 Freescale Semiconductor, Inc.