Information

42.3.2 Module Configuration Register (CANx_MCR)
This register defines global system configurations, such as the module operation modes
and the maximum message buffer configuration.
Addresses: CAN0_MCR is 4002_4000h base + 0h offset = 4002_4000h
CAN1_MCR is 400A_4000h base + 0h offset = 400A_4000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MDIS
FRZ
RFEN
HALT
NOTRDY
WAKMSK
SOFTRST
FRZACK
SUPV
SLFWAK
WRNEN
LPMACK
Reserved
DOZE
SRXDIS
IRMQ
W
Reset
1 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
LPRIOEN
AEN
0
IDAM
0
MAXMB
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
CANx_MCR field descriptions
Field Description
31
MDIS
Module Disable
This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN disables the clocks to the
CAN Protocol Engine and Controller Host Interface sub-modules. This is the only bit in MCR not affected
by soft reset.
0 Enable the FlexCAN module.
1 Disable the FlexCAN module.
30
FRZ
Freeze Enable
The FRZ bit specifies the FlexCAN behavior when the HALT bit in the MCR Register is set or when
Debug Mode is requested at MCU level. When FRZ is asserted, FlexCAN is enabled to enter Freeze
Mode. Negation of this bit field causes FlexCAN to exit from Freeze Mode.
0 Not enabled to enter Freeze Mode
1 Enabled to enter Freeze Mode
29
RFEN
Rx FIFO Enable
Table continues on the next page...
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1088 Freescale Semiconductor, Inc.