Information

CANx_CTRL1 field descriptions (continued)
Field Description
This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time. The valid programmable
values are 1–7. This field can only be written in Freeze mode as it is blocked by hardware in other modes.
Phase Buffer Segment 2 = (PSEG2 + 1) x Time-Quanta.
15
BOFFMSK
Bus Off Mask
This bit provides a mask for the Bus Off Interrupt.
0 Bus Off interrupt disabled
1 Bus Off interrupt enabled
14
ERRMSK
Error Mask
This bit provides a mask for the Error Interrupt.
0 Error interrupt disabled
1 Error interrupt enabled
13
CLKSRC
CAN Engine Clock Source
This bit selects the clock source to the CAN Protocol Engine (PE) to be either the peripheral clock (driven
by the PLL) or the crystal oscillator clock. The selected clock is the one fed to the prescaler to generate
the Serial Clock (Sclock). In order to guarantee reliable operation, this bit can only be written in Disable
mode as it is blocked by hardware in other modes. See Section "Protocol Timing".
0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock
frequency must be lower than the bus clock.
1 The CAN engine clock source is the peripheral clock.
12
LPB
Loop Back Mode
This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an internal
loop back that can be used for self test operation. The bit stream output of the transmitter is fed back
internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
recessive state (logic ‘1’). FlexCAN behaves as it normally does when transmitting, and treats its own
transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit
sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to
ensure proper reception of its own message. Both transmit and receive interrupts are generated. This bit
can only be written in Freeze mode as it is blocked by hardware in other modes.
NOTE: In this mode, the MCR[SRXDIS] cannot be asserted because this will impede the self reception
of a transmitted message.
0 Loop Back disabled
1 Loop Back enabled
11
TWRNMSK
Tx Warning Interrupt Mask
This bit provides a mask for the Tx Warning Interrupt associated with the TWRNINT flag in the Error and
Status Register. This bit is read as zero when MCR[WRNEN] bit is negated. This bit can only be written if
MCR[WRNEN] bit is asserted.
0 Tx Warning Interrupt disabled
1 Tx Warning Interrupt enabled
10
RWRNMSK
Rx Warning Interrupt Mask
Table continues on the next page...
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1094 Freescale Semiconductor, Inc.