Information

Addresses: CAN0_TIMER is 4002_4000h base + 8h offset = 4002_4008h
CAN1_TIMER is 400A_4000h base + 8h offset = 400A_4008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIMER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_TIMER field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–0
TIMER
Timer value
Contains the free-running counter value.
42.3.5 Rx Mailboxes Global Mask Register (CANx_RXMGMASK)
This register is located in RAM.
RXMGMASK is provided for legacy support.
• When the MCR[IRMQ] bit is negated, RXMGMASK is always in effect.
• When the MCR[IRMQ] bit is asserted, RXMGMASK has no effect.
RXMGMASK is used to mask the filter fields of all Rx MBs, excluding MBs 14-15,
which have individual mask registers.
This register can only be written in Freeze mode as it is blocked by hardware in other
modes.
Addresses: CAN0_RXMGMASK is 4002_4000h base + 10h offset = 4002_4010h
CAN1_RXMGMASK is 400A_4000h base + 10h offset = 400A_4010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MG[31:0]
W
Reset
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CANx_RXMGMASK field descriptions
Field Description
31–0
MG[31:0]
Rx Mailboxes Global Mask Bits
Chapter 42 CAN (FlexCAN)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1097