Information

Section Number Title Page
11.4.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................249
11.4.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................249
11.5 Functional description...................................................................................................................................................250
11.5.1 Pin control....................................................................................................................................................250
11.5.2 Global pin control........................................................................................................................................250
11.5.3 External interrupts........................................................................................................................................251
11.5.4 Digital filter..................................................................................................................................................252
Chapter 12
System integration module (SIM)
12.1 Introduction...................................................................................................................................................................253
12.1.1 Features........................................................................................................................................................253
12.1.2 Modes of operation......................................................................................................................................253
12.1.3 SIM Signal Descriptions..............................................................................................................................254
12.2 Memory map and register definition.............................................................................................................................254
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................256
12.2.2 System Options Register 2 (SIM_SOPT2)..................................................................................................258
12.2.3 System Options Register 4 (SIM_SOPT4)..................................................................................................260
12.2.4 System Options Register 5 (SIM_SOPT5)..................................................................................................263
12.2.5 System Options Register 6 (SIM_SOPT6)..................................................................................................264
12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................265
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................267
12.2.8 System Clock Gating Control Register 1 (SIM_SCGC1)............................................................................268
12.2.9 System Clock Gating Control Register 2 (SIM_SCGC2)............................................................................269
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)............................................................................270
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................271
12.2.12 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................273
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................275
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................278
12.2.15 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................279
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 11