Information

Addresses: CAN0_ECR is 4002_4000h base + 1Ch offset = 4002_401Ch
CAN1_ECR is 400A_4000h base + 1Ch offset = 400A_401Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RXERRCNT TXERRCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ECR field descriptions
Field Description
31–16
Reserved
This read-only field is reserved and always has the value zero.
15–8
RXERRCNT
Receive Error Counter
7–0
TXERRCNT
Transmit Error Counter
42.3.9 Error and Status 1 Register (CANx_ESR1)
This register reflects various error conditions, some general status of the device and it is
the source of interrupts to the CPU.
The CPU read action clears bits 15-10, therefore the reported error conditions (bits 15-10)
are those that occurred since the last time the CPU read this register. Bits 9-3 are status
bits.
The following table shows the FlexCAN state variables and their meanings. Other
combinations not shown in the table are reserved.
SYNCH IDLE TX RX FlexCAN State
0 0 0 0 Not synchronized to
CAN bus
1 1 x x Idle
1 0 1 0 Transmitting
1 0 0 1 Receiving
Chapter 42 CAN (FlexCAN)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1101