Information
Addresses: CAN0_ESR1 is 4002_4000h base + 20h offset = 4002_4020h
CAN1_ESR1 is 400A_4000h base + 20h offset = 400A_4020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SYNCH
TWRNINT
RWRNINT
W w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BIT1ERR
BIT0ERR
ACKERR
CRCERR
FRMERR
STFERR
TXWRN
RXWRN
IDLE
TX FLTCONF RX
BOFFINT
ERRINT
WAKINT
W
w1c w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ESR1 field descriptions
Field Description
31–19
Reserved
This read-only field is reserved and always has the value zero.
18
SYNCH
CAN Synchronization Status
This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate
in the communication process. It is set and cleared by the FlexCAN. See the table in the overall
CAN_ESR1 register description.
0 FlexCAN is not synchronized to the CAN bus.
1 FlexCAN is synchronized to the CAN bus.
17
TWRNINT
Tx Warning Interrupt Flag
If the WRNEN bit in MCR is asserted, the TWRNINT bit is set when the TXWRN flag transitions from ‘0’ to
‘1’, meaning that the Tx error counter reached 96. If the corresponding mask bit in the Control Register
(TWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’. When
WRNEN is negated, this flag is masked. CPU must clear this flag before disabling the bit. Otherwise it will
be set when the WRNEN is set again. Writing ‘0’ has no effect. This flag is not generated during “Bus Off”
state. This bit is not updated during Freeze mode.
0 No such occurrence
1 The Tx error counter transitioned from less than 96 to greater than or equal to 96.
16
RWRNINT
Rx Warning Interrupt Flag
If the WRNEN bit in MCR is asserted, the RWRNINT bit is set when the RXWRN flag transitions from ‘0’
to ‘1’, meaning that the Rx error counters reached 96. If the corresponding mask bit in the Control
Register (RWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to ‘1’.
When WRNEN is negated, this flag is masked. CPU must clear this flag before disabling the bit.
Table continues on the next page...
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1102 Freescale Semiconductor, Inc.