Information

CANx_ESR1 field descriptions (continued)
Field Description
Otherwise it will be set when the WRNEN is set again. Writing ‘0’ has no effect. This bit is not updated
during Freeze mode.
0 No such occurrence
1 The Rx error counter transitioned from less than 96 to greater than or equal to 96.
15
BIT1ERR
Bit1 Error
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
message.
NOTE: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node
sending a passive error flag that detects dominant bits.
0 No such occurrence
1 At least one bit sent as recessive is received as dominant.
14
BIT0ERR
Bit0 Error
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a
message.
0 No such occurrence
1 At least one bit sent as dominant is received as recessive.
13
ACKERR
Acknowledge Error
This bit indicates that an Acknowledge Error has been detected by the transmitter node, i.e., a dominant
bit has not been detected during the ACK SLOT.
0 No such occurrence
1 An ACK error occurred since last read of this register.
12
CRCERR
Cyclic Redundancy Check Error
This bit indicates that a CRC Error has been detected by the receiver node, i.e., the calculated CRC is
different from the received.
0 No such occurrence
1 A CRC error occurred since last read of this register.
11
FRMERR
Form Error
This bit indicates that a Form Error has been detected by the receiver node, i.e., a fixed-form bit field
contains at least one illegal bit.
0 No such occurrence
1 A Form Error occurred since last read of this register.
10
STFERR
Stuffing Error
This bit indicates that a Stuffing Error has been detected.
0 No such occurrence
1 A Stuffing Error occurred since last read of this register.
9
TXWRN
TX Error Warning
Table continues on the next page...
Chapter 42 CAN (FlexCAN)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1103