Information
Addresses: CAN0_IFLAG1 is 4002_4000h base + 30h offset = 4002_4030h
CAN1_IFLAG1 is 400A_4000h base + 30h offset = 400A_4030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BUF31TO8I[bit 8]
W
w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
BUF31TO8I[7:0]
BUF7I
BUF6I
BUF5I
BUF4TO0I
W
w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_IFLAG1 field descriptions
Field Description
31–8
BUF31TO8I
Buffer MB
i
Interrupt
Each bit flags the corresponding FlexCAN Message Buffer interrupt.
0 The corresponding buffer has no occurrence of successfully completed transmission or reception.
1 The corresponding buffer has successfully completed transmission or reception.
7
BUF7I
Buffer MB7 Interrupt or "Rx FIFO Overflow"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB7.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF7I flag represents "Rx FIFO Overflow" when MCR[RFEN] is set. In this case, the flag indicates
that a message was lost because the Rx FIFO is full. Note that the flag will not be asserted when the Rx
FIFO is full and the message was captured by a Mailbox.
0 No occurrence of MB7 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO
overflow (when MCR[RFEN]=1)
1 MB7 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO overflow (when
MCR[RFEN]=1)
6
BUF6I
Buffer MB6 Interrupt or "Rx FIFO Warning"
When the RFEN bit in the MCR is cleared (Rx FIFO disabled), this bit flags the interrupt for MB6.
NOTE: This flag is cleared by the FlexCAN whenever the bit MCR[RFEN] is changed by CPU writes.
The BUF6I flag represents "Rx FIFO Warning" when MCR[RFEN] is set. In this case, the flag indicates
when the number of unread messages within the Rx FIFO is increased to 5 from 4 due to the reception of
a new one, meaning that the Rx FIFO is almost full. Note that if the flag is cleared while the number of
unread messages is greater than 4, it does not assert again until the number of unread messages within
the Rx FIFO is decreased to be equal to or less than 4.
Table continues on the next page...
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1108 Freescale Semiconductor, Inc.