Information

3.7.1.3.1 ADC0 Channel Assignment for 144-Pin Package
ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
00000 DAD0 ADC0_DP0 and ADC0_DM0
1
ADC0_DP0
2
00001 DAD1 ADC0_DP1 and ADC0_DM1 ADC0_DP1
00010 DAD2 PGA0_DP and PGA0_DM PGA0_DP
00011 DAD3 ADC0_DP3 and ADC0_DM3
3
ADC0_DP3
4
00100
5
AD4a Reserved ADC0_SE4a
00101
5
AD5a Reserved ADC0_SE5a
00110
5
AD6a Reserved ADC0_SE6a
00111
5
AD7a Reserved ADC0_SE7a
00100
5
AD4b Reserved ADC0_SE4b
00101
5
AD5b Reserved ADC0_SE5b
00110
5
AD6b Reserved ADC0_SE6b
00111
5
AD7b Reserved ADC0_SE7b
01000 AD8 Reserved ADC0_SE8
6
01001 AD9 Reserved ADC0_SE9
7
01010 AD10 Reserved ADC0_SE10
01011 AD11 Reserved ADC0_SE11
01100 AD12 Reserved ADC0_SE12
01101 AD13 Reserved ADC0_SE13
01110 AD14 Reserved ADC0_SE14
01111 AD15 Reserved ADC0_SE15
10000 AD16 Reserved ADC0_SE16
10001 AD17 Reserved ADC0_SE17
10010 AD18 Reserved ADC0_SE18
10011 AD19 Reserved ADC0_DM0
8
10100 AD20 Reserved ADC0_DM1
10101 AD21 Reserved
10110 AD22 Reserved
10111 AD23 Reserved 12-bit DAC0 Output
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff)
9
Bandgap (S.E)
9
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
1. Interleaved with ADC1_DP3 and ADC1_DM3
2. Interleaved with ADC1_DP3
3. Interleaved with ADC1_DP0 and ADC1_DM0
4. Interleaved with ADC1_DP0
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 111