Information

CANx_CTRL2 field descriptions (continued)
Field Description
The number of remaining Mailboxes available will be:
(SETUP_MB - 8) - (RFFN x 2)
If the Number of Rx FIFO Filters programmed through RFFN exceeds the SETUP_MB value
(memory space available) the exceeding ones will not be functional.
RFFN[3:
0]
Number
of Rx
FIFO
filters
Message
Buffers
occupied by Rx
FIFO and ID
Filter Table
Remaining
Available
Mailboxes
1
Rx FIFO ID Filter
Table Elements
Affected by Rx
Individual Masks
2
Rx FIFO ID Filter
Table Elements
Affected by Rx
FIFO Global Mask
2
0x0 8 MB 0-7 MB 8-63 Elements 0-7 none
0x1 16 MB 0-9 MB 10-63 Elements 0-9 Elements 10-15
0x2 24 MB 0-11 MB 12-63 Elements 0-11 Elements 12-23
0x3 32 MB 0-13 MB 14-63 Elements 0-13 Elements 14-31
0x4 40 MB 0-15 MB 16-63 Elements 0-15 Elements 16-39
0x5 48 MB 0-17 MB 18-63 Elements 0-17 Elements 18-47
0x6 56 MB 0-19 MB 20-63 Elements 0-19 Elements 20-55
0x7 64 MB 0-21 MB 22-63 Elements 0-21 Elements 22-63
0x8 72 MB 0-23 MB 24-63 Elements 0-23 Elements 24-71
0x9 80 MB 0-25 MB 26-63 Elements 0-25 Elements 26-79
0xA 88 MB 0-27 MB 28-63 Elements 0-27 Elements 28-87
0xB 96 MB 0-29 MB 30-63 Elements 0-29 Elements 30-95
0xC 104 MB 0-31 MB 32-63 Elements 0-31 Elements 32-103
0xD 112 MB 0-33 MB 34-63 Elements 0-31 Elements 32-111
0xE 120 MB 0-35 MB 36-63 Elements 0-31 Elements 32-119
0xF 128 MB 0-37 MB 38-63 Elements 0-31 Elements 32-127
1. The number of the last remaining available mailboxes is defined by the least value between the
parameter NUMBER_OF_MB minus 1 and the MCR[MAXMB] field.
2. If Rx Individual Mask Registers are not enabled then all Rx FIFO filters are affected by the Rx FIFO
Global Mask.
23–19
TASD
Tx Arbitration Start Delay
This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the
first bit of CRC field on CAN bus. This field can only be written in Freeze mode as it is blocked by
hardware in other modes.
This field is useful to optimize the transmit performance based on factors such as: peripheral/serial clock
ratio, CAN bit timing and number of MBs. The duration of an arbitration process, in terms of CAN bits, is
directly proportional to the number of available MBs and CAN baud rate and inversely proportional to the
peripheral clock frequency.
The optimal arbitration timing is that in which the last MB is scanned right before the first bit of the
Intermission field of a CAN frame. Therefore, if there are few MBs and the system/serial clock ratio is high
and the CAN baud rate is low then the arbitration can be delayed and vice-versa.
Table continues on the next page...
Chapter 42 CAN (FlexCAN)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1111