Information

5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
6. Interleaved with ADC1_SE8
7. Interleaved with ADC1_SE9
8. Interleaved with ADC1_DM3
9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this
ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data
sheet for the bandgap voltage (V
BG
) specification.
3.7.1.4 ADC1 Connections/Channel Assignment
NOTE
As indicated in the following tables, each ADCx_DPx input
and certain ADCx_DMx inputs may operate as single-ended
ADC channels in single-ended mode.
3.7.1.4.1 ADC1 Channel Assignment for 144-Pin Package
ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
00000 DAD0 ADC1_DP0 and ADC1_DM0
1
ADC1_DP0
2
00001 DAD1 ADC1_DP1 and ADC1_DM1 ADC1_DP1
00010 DAD2 PGA1_DP and PGA1_DM PGA1_DP
00011 DAD3 ADC1_DP3 and ADC1_DM3
3
ADC1_DP3
4
00100
5
AD4a Reserved ADC1_SE4a
00101
5
AD5a Reserved ADC1_SE5a
00110
5
AD6a Reserved ADC1_SE6a
00111
5
AD7a Reserved ADC1_SE7a
00100
5
AD4b Reserved ADC1_SE4b
00101
5
AD5b Reserved ADC1_SE5b
00110
5
AD6b Reserved ADC1_SE6b
00111
5
AD7b Reserved ADC1_SE7b
01000 AD8 Reserved ADC1_SE8
6
01001 AD9 Reserved ADC1_SE9
7
01010 AD10 Reserved ADC1_SE10
01011 AD11 Reserved ADC1_SE11
01100 AD12 Reserved ADC1_SE12
01101 AD13 Reserved ADC1_SE13
01110 AD14 Reserved ADC1_SE14
01111 AD15 Reserved ADC1_SE15
10000 AD16 Reserved ADC1_SE16
10001 AD17 Reserved ADC1_SE17
10010 AD18 Reserved VREF Output
Table continues on the next page...
Analog
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
112 Freescale Semiconductor, Inc.