Information

ADC Channel
(SC1n[ADCH])
Channel Input signal
(SC1n[DIFF]= 1)
Input signal
(SC1n[DIFF]= 0)
10011 AD19 Reserved ADC1_DM0
8
10100 AD20 Reserved ADC1_DM1
10101 AD21 Reserved Reserved
10110 AD22 Reserved
10111 AD23 Reserved 12-bit DAC1 Output
11000 AD24 Reserved Reserved
11001 AD25 Reserved Reserved
11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E)
11011 AD27 Bandgap (Diff)
9
Bandgap (S.E)
9
11100 AD28 Reserved Reserved
11101 AD29 -VREFH (Diff) VREFH (S.E)
11110 AD30 Reserved VREFL
11111 AD31 Module Disabled Module Disabled
1. Interleaved with ADC0_DP3 and ADC0_DM3
2. Interleaved with ADC0_DP3
3. Interleaved with ADC0_DP0 and ADC0_DM0
4. Interleaved with ADC0_DP0
5. ADCx_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b. Refer to MUXSEL description in ADC chapter
for details.
6. Interleaved with ADC0_SE8
7. Interleaved with ADC0_SE9
8. Interleaved with ADC0_DM3
9. This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this
ADC channel, ensure that you enable the bandgap buffer by setting the PMC_REGSC[BGBE] bit. Refer to the device data
sheet for the bandgap voltage (V
BG
) specification.
3.7.1.5 ADC Channels MUX Selection
The following figure shows the assignment of ADCx_SEn channels a and b through a
MUX selection to ADC. To select between alternate set of channels, refer to
ADCx_CFG2[MUXSEL] bit settings for more details.
AD5 [00101]
ADCx_SE4a
ADCx_SE5a
ADCx_SE6a
ADCx_SE7a
ADCx_SE4b
ADCx_SE5b
ADCx_SE6b
ADCx_SE7b
AD4 [00100]
AD6 [00110]
AD7 [00111]
ADC
Figure 3-35. ADCx_SEn channels a and b selection
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 113