Information

3.7.1.8 ADC triggers
The ADC supports both software and hardware triggers. The primary hardware
mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other
peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The
PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions
in run mode (where PDB is enabled). On the other hand, the ADC can conduct
conversions in low power modes, not triggered by PDB. This allows the ADC to do
conversions in low power mode and store the output in the result register. The ADC
generates interrupt when the data is ready in the result register that wakes the system
from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits
in the SOPT7 register.
For operation of triggers in different modes, refer to Power Management chapter.
3.7.1.9 Alternate clock
For this device, the alternate clock is connected to OSCERCLK.
NOTE
This clock option is only usable when OSCERCLK is in the
MHz range. A system with OSCERCLK in the kHz range has
the optional clock source below minimum ADC clock operating
frequency.
3.7.1.10 ADC low-power modes
This table shows the ADC low-power modes and the corresponding chip low-power
modes.
Table 3-45. ADC low-power modes
Module mode Chip mode
Wait Wait, VLPW
Normal Stop Stop, VLPS
Low Power Stop LLS, VLLS3, VLLS2, VLLS1
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 115