Information

concurrent memory access due to the CPU or other internal
peripheral.
When doing matching and arbitration, FlexCAN needs to scan the whole Message Buffer
memory during the available time slot. In order to have sufficient time to do that, the
following requirements must be observed:
• A valid CAN bit timing must be programmed, as indicated in Table 42-119
• The peripheral clock frequency can not be smaller than the oscillator clock
frequency, i.e. the PLL can not be programmed to divide down the oscillator clock;
see Clock domains and restrictions
• There must be a minimum ratio between the peripheral clock frequency and the CAN
bit rate, as specified in the following table
Table 42-120. Minimum Ratio Between Peripheral Clock Frequency and
CAN Bit Rate
Number of Message Buffers RFEN
Minimum Number of Peripheral
Clocks per CAN bit
16 and 32 0 16
64 0 25
16 1 16
32 1 17
64 1 30
A direct consequence of the first requirement is that the minimum number of time quanta
per CAN bit must be 8, so the oscillator clock frequency should be at least 8 times the
CAN bit rate. The minimum frequency ratio specified in the preceding table can be
achieved by choosing a high enough peripheral clock frequency when compared to the
oscillator clock frequency, or by adjusting one or more of the bit timing parameters
(PRESDIV, PROPSEG, PSEG1, PSEG2) contained in the Control 1 Register (CTRL1).
In case of synchronous operation (when the peripheral clock frequency is equal to the
oscillator clock frequency), the number of peripheral clocks per CAN bit can be adjusted
by selecting an adequate value for PRESDIV in order to meet the requirement in the
preceding table. In case of asynchronous operation (the peripheral clock frequency
greater than the oscillator clock frequency), the number of peripheral clocks per CAN bit
can be adjusted by both PRESDIV and/or the frequency ratio.
Chapter 42 CAN (FlexCAN)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1151