Information

3.7.1.11 PGA Integration
• No additional external pins are required for the PGA as it is part of the ADC and is
selected as a separate channel
• Each PGA connects to the differential ADC channels
• The PGA outputs differential pairs that are connected to ADC differential input
• When the PGA is used, differential input from the pins is connected to differential
input channel 2 on ADCx
ADC0
DAD1
DAD0
DAD2
DAD3
ADC1
DAD3
DAD2
DAD0
DAD1
PGA1
PGA0
PGA0_DP/ADC0_DP0/ADC1_DP3
PGA0_DM/ADC0_DM0/ADC1_DM3
PGA1_DP/ADC1_DP0/ADC0_DP3
PGA1_DM/ADC1_DM0/ADC0_DM3
ADC1_DP1
ADC1_DM1
ADC0_DP1
ADC0_DM1
Figure 3-37. PGA Integration
3.7.2 CMP Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Analog
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
116 Freescale Semiconductor, Inc.