Information

Baud Rate, Delay &
Transfer Control
Shift Register
SPI
SCK
S PI
32
Data
Data
TX FIFO
Slave Bus Interface
Clock/Reset
POPR
eDMA
INTC
DMA and Interrupt Control
PUSHR
RX FIFO
CMD
32
8
PCS[x]/SS/PCSS
SIN
SOUT
Figure 43-1. DSPI Block Diagram
43.1.2 Features
The DSPI supports these SPI features:
• Full-duplex, Four-wire synchronous transfers
• Master and slave modes
• Data streaming operation in slave mode with continuous slave selection
• Buffered transmit operation using the TX FIFO with depth of 4 entries
• Buffered receive operation using the RX FIFO with depth of 4 entries
• TX and RX FIFOs can be disabled individually for low-latency updates to SPI
queues
• Visibility into TX and RX FIFOs for ease of debugging
• Programmable transfer attributes on a per-frame basis:
Introduction
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1162 Freescale Semiconductor, Inc.