Information

• 2 transfer attribute registers
• Serial clock with programmable polarity and phase
• Various programmable delays
• Programmable serial frame size of 4 to 16 bits, expandable by software control
• SPI frames longer than 16 bits can be supported using the continuous
selection format.
• Continuously held chip select capability
• 6 Peripheral Chip Selects, expandable to 64 with external demultiplexer
• Deglitching support for up to 32 Peripheral Chip Select with external demultiplexer
• DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
• TX FIFO is not full (TFFF)
• RX FIFO is not empty (RFDF)
• Interrupt conditions:
• End of queue reached (EOQF)
• TX FIFO is not full (TFFF)
• Transfer of current frame complete (TCF)
• Attempt to transmit with an empty Transmit FIFO (TFUF)
• RX FIFO is not empty (RFDF)
• Frame received while Receive FIFO is full (RFOF)
• Global interrupt request line
• Modified SPI transfer formats for communication with slower peripheral devices
• Power-saving architectural features
• Support for stop mode
• Support for doze mode
43.1.3 DSPI Configurations
The DSPI module always operates in SPI configuration.
Chapter 43 SPI (DSPI)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1163