Information

43.1.3.1 SPI Configuration
The SPI configuration allows the DSPI to send and receive serial data. This configuration
allows the DSPI to operate as a basic SPI block with internal FIFOs supporting external
queues operation. Transmit data and received data reside in separate FIFOs. The host
CPU or a DMA controller read the received data from the receive FIFO and write
transmit data to the transmit FIFO.
For queued operations the SPI queues can reside in system RAM, external to the DSPI.
Data transfers between the queues and the DSPI FIFOs are accomplished by a DMA
controller or host CPU. The following figure shows a system example with DMA, DSPI
and external queues in system RAM.
System RAM
DSPI
DMA Controller
TX Queue
RX FIFO
TX FIFO
Shift Register
Addr/Ctrl
RX Queue
Addr/Ctrl
Req
Data
Data
Done
Data
Data
Figure 43-2. DSPI with Queues and DMA
43.1.4 Modes of Operation
The DSPI supports the following modes of operation that can be divided into two
categories;
• Module-specific modes:
• Master mode
• Slave mode
• Module disable mode
• MCU-specific modes:
Introduction
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1164 Freescale Semiconductor, Inc.