Information

Signal multiplexing
Module signals
Register
access
CMP
Peripheral
bridge 0
Other peripherals
Figure 3-38. CMP configuration
Table 3-46. Reference links to related information
Topic Related module Reference
Full description Comparator (CMP) Comparator
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.7.2.1 CMP input connections
The following table shows the fixed internal connections to the CMP.
CMP Inputs CMP0 CMP1 CMP2
IN0 CMP0_IN0 CMP1_IN0 CMP2_IN0
IN1 CMP0_IN1 CMP1_IN1 CMP2_IN1
IN2 CMP0_IN2 — —
IN3 CMP0_IN3 12b DAC0 reference/
CMP1_IN3
12b DAC1 reference/
CMP2_IN3
IN4 CMP0_IN4 — —
IN5 VREF output/CMP0_IN5 VREF output/CMP1_IN5 —CMP2_IN5
IN6 Bandgap Bandgap Bandgap
IN7 6b DAC0 reference 6b DAC1 reference —
3.7.2.2 CMP external references
The 6-bit DAC sub-block supports selection of two references. For this device, the
references are connected as follows:
• VREF_OUT - V
in1
input
• VDD - V
in2
input
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 117