Information

SPI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400A_C000 DSPI Module Configuration Register (SPI2_MCR) 32 R/W 0000_4001h
43.3.1/
1171
400A_C008 DSPI Transfer Count Register (SPI2_TCR) 32 R/W 0000_0000h
43.3.2/
1174
400A_C00C
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI2_CTAR0)
32 R/W 7800_0000h
43.3.3/
1174
400A_C00C
DSPI Clock and Transfer Attributes Register (In Slave
Mode) (SPI2_CTAR0_SLAVE)
32 R/W 7800_0000h
43.3.4/
1179
400A_C010
DSPI Clock and Transfer Attributes Register (In Master
Mode) (SPI2_CTAR1)
32 R/W 7800_0000h
43.3.3/
1174
400A_C02C DSPI Status Register (SPI2_SR) 32 R/W See section
43.3.5/
1180
400A_C030
DSPI DMA/Interrupt Request Select and Enable Register
(SPI2_RSER)
32 R/W 0000_0000h
43.3.6/
1183
400A_C034
DSPI PUSH TX FIFO Register In Master Mode
(SPI2_PUSHR)
32 R/W 0000_0000h
43.3.7/
1185
400A_C034
DSPI PUSH TX FIFO Register In Slave Mode
(SPI2_PUSHR_SLAVE)
32 R/W 0000_0000h
43.3.8/
1187
400A_C038 DSPI POP RX FIFO Register (SPI2_POPR) 32 R 0000_0000h
43.3.9/
1187
400A_C03C DSPI Transmit FIFO Registers (SPI2_TXFR0) 32 R 0000_0000h
43.3.10/
1188
400A_C040 DSPI Transmit FIFO Registers (SPI2_TXFR1) 32 R 0000_0000h
43.3.10/
1188
400A_C044 DSPI Transmit FIFO Registers (SPI2_TXFR2) 32 R 0000_0000h
43.3.10/
1188
400A_C048 DSPI Transmit FIFO Registers (SPI2_TXFR3) 32 R 0000_0000h
43.3.10/
1188
400A_C07C DSPI Receive FIFO Registers (SPI2_RXFR0) 32 R 0000_0000h
43.3.11/
1188
400A_C080 DSPI Receive FIFO Registers (SPI2_RXFR1) 32 R 0000_0000h
43.3.11/
1188
400A_C084 DSPI Receive FIFO Registers (SPI2_RXFR2) 32 R 0000_0000h
43.3.11/
1188
400A_C088 DSPI Receive FIFO Registers (SPI2_RXFR3) 32 R 0000_0000h
43.3.11/
1188
Memory Map/Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1170 Freescale Semiconductor, Inc.