Information

SPIx_MCR field descriptions (continued)
Field Description
13
DIS_TXF
Disable Transmit FIFO
When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI.
This bit can only be written when the MDIS bit is cleared.
0 Tx FIFO is enabled.
1 Tx FIFO is disabled.
12
DIS_RXF
Disable Receive FIFO
When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI.
This bit can only be written when the MDIS bit is cleared.
0 Rx FIFO is enabled.
1 Rx FIFO is disabled.
11
CLR_TXF
Clear TX FIFO
Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The CLR_TXF bit is always
read as zero.
0 Do not clear the Tx FIFO counter.
1 Clear the Tx FIFO counter.
10
CLR_RXF
Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The CLR_RXF bit is always read
as zero.
0 Do not clear the Rx FIFO counter.
1 Clear the Rx FIFO counter.
9–8
SMPL_PT
Sample Point
Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid only when
CPHA bit in CTAR register is 0.
00 0 system clocks between SCK edge and SIN sample
01 1 system clock between SCK edge and SIN sample
10 2 system clocks between SCK edge and SIN sample
11 Reserved
7–2
Reserved
This read-only field is reserved and always has the value zero.
1
Reserved
This read-only field is reserved and always has the value zero.
0
HALT
Halt
Starts and stops DSPI transfers.
0 Start transfers.
1 Stop transfers.
Chapter 43 SPI (DSPI)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1173