Information

43.3.6 DSPI DMA/Interrupt Request Select and Enable Register
(SPIx_RSER)
RSER controls DMA and interrupt requests. Do not write to the RSER while the DSPI is
in the Running state.
Addresses: SPI0_RSER is 4002_C000h base + 30h offset = 4002_C030h
SPI1_RSER is 4002_D000h base + 30h offset = 4002_D030h
SPI2_RSER is 400A_C000h base + 30h offset = 400A_C030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
TCF_RE
0 0
EOQF_RE
TFUF_RE
0
TFFF_RE
TFFF_DIRS
0 0 0 0
RFOF_RE
0
RFDF_RE
RFDF_DIRS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPIx_RSER field descriptions
Field Description
31
TCF_RE
Transmission Complete Request Enable
Enables TCF flag in the SR to generate an interrupt request.
0 TCF interrupt requests are disabled.
1 TCF interrupt requests are enabled.
30
Reserved
This read-only field is reserved and always has the value zero.
29
Reserved
This read-only field is reserved and always has the value zero.
28
EOQF_RE
DSPI Finished Request Enable
Enables the EOQF flag in the SR to generate an interrupt request.
0 EOQF interrupt requests are disabled.
1 EOQF interrupt requests are enabled.
27
TFUF_RE
Transmit FIFO Underflow Request Enable
Enables the TFUF flag in the SR to generate an interrupt request.
0 TFUF interrupt requests are disabled.
1 TFUF interrupt requests are enabled.
Table continues on the next page...
Chapter 43 SPI (DSPI)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1183