Information

Generally more than one slave device can be connected to the DSPI master. 6 Peripheral
Chip Select (PCS) signals of the DSPI masters can be used to select which of the slaves
to communicate with. Refer to the chip configuration chapter for the number of PCS
signals used in this MCU.
The three DSPI configurations share transfer protocol and timing properties which are
described independently of the configuration in Transfer Formats . The transfer rate and
delay settings are described in DSPI Baud Rate and Clock Delay Generation.
43.4.1 Start and Stop of DSPI Transfers
The DSPI has two operating states: STOPPED and RUNNING. The states are
independent of DSPI configuration. The default state of the DSPI is STOPPED. In the
STOPPED state no serial transfers are initiated in master mode and no transfers are
responded to in slave mode. The STOPPED state is also a safe state for writing the
various configuration registers of the DSPI without causing undetermined results. In the
RUNNING state serial transfers take place.
The TXRXS bit in the SR indicates what state the DSPI in. The bit is set if the module in
RUNNING state.
The DSPI is started (DSPI transitions to RUNNING) when all of the following conditions
are true:
• SR[EOQF] bit is clear
• MCU is not in the debug mode or the MCR[FRZ] bit is clear
• MCR[HALT] bit is clear
The DSPI stops (transitions from RUNNING to STOPPED) after the current frame when
any one of the following conditions exist:
• SR[EOQF] bit is set
• MCU in the debug mode and the MCR[FRZ] bit is set
• MCR[HALT] bit is set
State transitions from RUNNING to STOPPED occur on the next frame boundary if a
transfer is in progress, or immediately if no transfers are in progress.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1190 Freescale Semiconductor, Inc.