Information

43.4.3.5 Peripheral Chip Select Strobe Enable (PCSS )
The PCSS signal provides a delay to allow the PCS signals to settle after a transition
occurs thereby avoiding glitches. When the DSPI is in master mode and the PCSSE bit is
set in the MCR, PCSS provides a signal for an external demultiplexer to decode the
PCS[0] - PCS[4] signals into as many as 128 glitch-free PCS signals. The following
figure shows the timing of the PCSS signal relative to PCS signals.
t
PCSSCK
PCSS
PCSx
t
PASC
Figure 43-93. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS signals and the assertion of
PCSS is selected
by the PCSSCK field in the CTAR based on the following formula:
At the end of the transfer the delay between PCSS negation and PCS negation is selected
by the PASC field in the CTAR based on the following formula:
The following table shows an example of how to compute the t
pcssck
delay.
Table 43-110. Peripheral Chip Select Strobe Assert Computation Example
f
sys
PCSSCK Prescaler Delay before Transfer
100 MHz 0b11 7 70.0 ns
The following table shows an example of how to compute the t
pasc
delay.
Table 43-111. Peripheral Chip Select Strobe Negate Computation Example
f
sys
PASC Prescaler Delay after Transfer
100 MHz 0b11 7 70.0 ns
The PCSS signal is not supported when Continuous Serial Communication SCK mode
are enabled.
Chapter 43 SPI (DSPI)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1197