Information

The voltage reference can provide a reference voltage to external peripherals or a

reference to analog peripherals, such as the ADC, DAC, or CMP.

NOTE

For either an internal or external reference if the VREF_OUT

functionality is being used, VREF_OUT signal must be

connected to an output load capacitor. Refer the device data

sheet for more details.

Timers

3.8.1 PDB Configuration

This section summarizes how the module has been configured in the chip. For a

comprehensive description of the module itself, see the module’s dedicated chapter.

Signal multiplexing

Module signals

access

PDB

Peripheral bus

controller 0

Other peripherals

Transfers

Figure 3-41. PDB configuration

Table 3-49. Reference links to related information

Topic Related module Reference

Full description PDB PDB

System memory map System memory map

Clocking Clock distribution

Power management Power management

Signal multiplexing Port control Signal multiplexing

3.8.1.1 PDB Instantiation

3.8

Timers

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

120 Freescale Semiconductor, Inc.