Information

I2Cx_C1 field descriptions (continued)
Field Description
0 Disabled
1 Enabled
6
IICIE
I2C interrupt enable
Enables I2C interrupt requests.
0 Disabled
1 Enabled
5
MST
Master mode select
When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master mode
is selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operation
changes from master to slave.
0 Slave mode
1 Master mode
4
TX
Transmit mode select
Selects the direction of master and slave transfers. In master mode this bit must be set according to the
type of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slave
this bit must be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
3
TXAK
Transmit acknowledge enable
Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave
receivers. The value of the FACK bit affects NACK/ACK generation.
0 An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is
set) receiving byte.
1 No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is
set) receiving data byte.
NOTE: SCL is held low until TXAK is written.
2
RSTA
Repeat START
Writing a one to this bit generates a repeated START condition provided it is the current master. This bit
will always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration.
1
WUEN
Wakeup enable
The I2C module can wake the MCU from low power mode with no peripheral bus running when slave
address matching occurs.
0 Normal operation. No interrupt generated when address matching in low power mode.
1 Enables the wakeup function in low power mode.
0
DMAEN
DMA enable
The DMAEN bit enables or disables the DMA function.
Table continues on the next page...
Chapter 44 Inter-Integrated Circuit (I2C)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1221