Information

I2Cx_S field descriptions (continued)
Field Description
0 Not addressed
1 Addressed as a slave
5
BUSY
Bus busy
Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is
detected and cleared when a STOP signal is detected.
0 Bus is idle
1 Bus is busy
4
ARBL
Arbitration lost
This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by
software, by writing a one to it.
0 Standard bus operation.
1 Loss of arbitration.
3
RAM
Range address match
This bit is set by any of the following conditions:
• Any nonzero calling address is received that matches the address in the RA register.
• The RMEN bit is set and the calling address is within the range of values of the A1 and RA
registers.
Writing the C1 register with any value clears this bit.
0 Not addressed
1 Addressed as a slave
2
SRW
Slave read/write
When addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sent
to the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
1
IICIF
Interrupt flag
This bit sets when an interrupt is pending. This bit must be cleared by software or by writing a 1 to it in the
interrupt routine. One of the following events can set this bit:
• One byte transfer including ACK/NACK bit completes if FACK = 0
• One byte transfer excluding ACK/NACK bit completes if FACK = 1. An ACK or NACK is sent on the
bus by writing 0 or 1 to TXAK after this bit is set in receive mode
• Match of slave address to calling address including primary slave address, range slave address,
alert response address, second slave address, or general call address.
• Arbitration lost
• In SMBus mode, any timeouts except SCL and SDA high timeouts
0 No interrupt pending
1 Interrupt pending
0
RXAK
Receive acknowledge
Table continues on the next page...
Chapter 44 Inter-Integrated Circuit (I2C)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1223