Information

44.3.9 I2C SMBus Control and Status register (I2Cx_SMB)
NOTE
When the SCL and SDA signals are held high for a length of
time greater than the high timeout period, the SHTF1 flag sets.
Before reaching this threshold, while the system is detecting
how long these signals are being held high, a master assumes
that the bus is free. However, the SHTF1 bit rises in the bus
transmission process with the idle bus state.
NOTE
When the TCKSEL bit is set, there is no meaning to monitor
the SHTF1 bit because the bus speed is too high to match the
protocol of SMBus.
Addresses: I2C0_SMB is 4006_6000h base + 8h offset = 4006_6008h
I2C1_SMB is 4006_7000h base + 8h offset = 4006_7008h
Bit 7 6 5 4 3 2 1 0
Read
FACK ALERTEN SIICAEN TCKSEL
SLTF SHTF1 SHTF2
SHTF2IE
Write w1c w1c
Reset
0 0 0 0 0 0 0 0
I2Cx_SMB field descriptions
Field Description
7
FACK
Fast NACK/ACK enable
For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the
result of receiving data byte.
0 An ACK or NACK is sent on the following receiving data byte
1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a
data byte generates a NACK.
6
ALERTEN
SMBus alert response address enable
Enables or disables SMBus alert response address matching.
NOTE: After the host responds to a device that used the alert response address, you must use software
to put the device's address on the bus. The alert protocol is described in the SMBus
specification.
0 SMBus alert response address matching is disabled
1 SMBus alert response address matching is enabled
5
SIICAEN
Second I2C address enable
Enables or disables SMBus device default address.
Table continues on the next page...
Chapter 44 Inter-Integrated Circuit (I2C)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1227