Information

I2Cx_SMB field descriptions (continued)
Field Description
0 I2C address register 2 matching is disabled
1 I2C address register 2 matching is enabled
4
TCKSEL
Timeout counter clock select
Selects the clock source of the timeout counter.
0 Timeout counter counts at the frequency of the bus clock / 64
1 Timeout counter counts at the frequency of the bus clock
3
SLTF
SCL low timeout flag
This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-
zero value (LoValue) and an SCL low timeout occurs. Software clears this bit by writing a logic 1 to it.
NOTE: The low timeout function is disabled when the SLT register's value is zero.
0 No low timeout occurs
1 Low timeout occurs
2
SHTF1
SCL high timeout flag 1
This read-only bit sets when SCL and SDA are held high more than clock × LoValue / 512, which
indicates the bus is free. This bit is cleared automatically.
0 No SCL high and SDA high timeout occurs
1 SCL high and SDA high timeout occurs
1
SHTF2
SCL high timeout flag 2
This bit sets when SCL is held high and SDA is held low more than clock × LoValue/512. Software clears
this bit by writing a 1 to it.
0 No SCL high and SDA low timeout occurs
1 SCL high and SDA low timeout occurs
0
SHTF2IE
SHTF2 interrupt enable
Enables SCL high and SDA low timeout interrupt.
0 SHTF2 interrupt is disabled
1 SHTF2 interrupt is enabled
44.3.10 I2C Address Register 2 (I2Cx_A2)
Addresses: I2C0_A2 is 4006_6000h base + 9h offset = 4006_6009h
I2C1_A2 is 4006_7000h base + 9h offset = 4006_7009h
Bit 7 6 5 4 3 2 1 0
Read
SAD
0
Write
Reset
1 1 0 0 0 0 1 0
Memory Map and Register Descriptions
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1228 Freescale Semiconductor, Inc.