Information

UART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A000 UART Baud Rate Registers:High (UART0_BDH) 8 R/W 00h
45.3.1/
1261
4006_A001 UART Baud Rate Registers: Low (UART0_BDL) 8 R/W 04h
45.3.2/
1262
4006_A002 UART Control Register 1 (UART0_C1) 8 R/W 00h
45.3.3/
1263
4006_A003 UART Control Register 2 (UART0_C2) 8 R/W 00h
45.3.4/
1265
4006_A004 UART Status Register 1 (UART0_S1) 8 R C0h
45.3.5/
1267
4006_A005 UART Status Register 2 (UART0_S2) 8 R/W 00h
45.3.6/
1270
4006_A006 UART Control Register 3 (UART0_C3) 8 R/W 00h
45.3.7/
1272
4006_A007 UART Data Register (UART0_D) 8 R/W 00h
45.3.8/
1273
4006_A008 UART Match Address Registers 1 (UART0_MA1) 8 R/W 00h
45.3.9/
1275
4006_A009 UART Match Address Registers 2 (UART0_MA2) 8 R/W 00h
45.3.10/
1275
4006_A00A UART Control Register 4 (UART0_C4) 8 R/W 00h
45.3.11/
1276
4006_A00B UART Control Register 5 (UART0_C5) 8 R/W 00h
45.3.12/
1277
4006_A00C UART Extended Data Register (UART0_ED) 8 R 00h
45.3.13/
1278
4006_A00D UART Modem Register (UART0_MODEM) 8 R/W 00h
45.3.14/
1279
4006_A00E UART Infrared Register (UART0_IR) 8 R/W 00h
45.3.15/
1280
4006_A010 UART FIFO Parameters (UART0_PFIFO) 8 R/W See section
45.3.16/
1281
4006_A011 UART FIFO Control Register (UART0_CFIFO) 8 R/W 00h
45.3.17/
1283
4006_A012 UART FIFO Status Register (UART0_SFIFO) 8 R/W C0h
45.3.18/
1284
4006_A013 UART FIFO Transmit Watermark (UART0_TWFIFO) 8 R/W 00h
45.3.19/
1285
4006_A014 UART FIFO Transmit Count (UART0_TCFIFO) 8 R 00h
45.3.20/
1286
Table continues on the next page...
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1252 Freescale Semiconductor, Inc.