Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400E_B005 UART Status Register 2 (UART5_S2) 8 R/W 00h
45.3.6/
1270
400E_B006 UART Control Register 3 (UART5_C3) 8 R/W 00h
45.3.7/
1272
400E_B007 UART Data Register (UART5_D) 8 R/W 00h
45.3.8/
1273
400E_B008 UART Match Address Registers 1 (UART5_MA1) 8 R/W 00h
45.3.9/
1275
400E_B009 UART Match Address Registers 2 (UART5_MA2) 8 R/W 00h
45.3.10/
1275
400E_B00A UART Control Register 4 (UART5_C4) 8 R/W 00h
45.3.11/
1276
400E_B00B UART Control Register 5 (UART5_C5) 8 R/W 00h
45.3.12/
1277
400E_B00C UART Extended Data Register (UART5_ED) 8 R 00h
45.3.13/
1278
400E_B00D UART Modem Register (UART5_MODEM) 8 R/W 00h
45.3.14/
1279
400E_B00E UART Infrared Register (UART5_IR) 8 R/W 00h
45.3.15/
1280
400E_B010 UART FIFO Parameters (UART5_PFIFO) 8 R/W See section
45.3.16/
1281
400E_B011 UART FIFO Control Register (UART5_CFIFO) 8 R/W 00h
45.3.17/
1283
400E_B012 UART FIFO Status Register (UART5_SFIFO) 8 R/W C0h
45.3.18/
1284
400E_B013 UART FIFO Transmit Watermark (UART5_TWFIFO) 8 R/W 00h
45.3.19/
1285
400E_B014 UART FIFO Transmit Count (UART5_TCFIFO) 8 R 00h
45.3.20/
1286
400E_B015 UART FIFO Receive Watermark (UART5_RWFIFO) 8 R/W 01h
45.3.21/
1286
400E_B016 UART FIFO Receive Count (UART5_RCFIFO) 8 R 00h
45.3.22/
1287
400E_B018 UART 7816 Control Register (UART5_C7816) 8 R/W 00h
45.3.23/
1288
400E_B019 UART 7816 Interrupt Enable Register (UART5_IE7816) 8 R/W 00h
45.3.24/
1289
400E_B01A UART 7816 Interrupt Status Register (UART5_IS7816) 8 R/W 00h
45.3.25/
1291
Table continues on the next page...
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1260 Freescale Semiconductor, Inc.