Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400E_B01B UART 7816 Wait Parameter Register (UART5_WP7816T0) 8 R/W 0Ah
45.3.26/
1293
400E_B01B UART 7816 Wait Parameter Register (UART5_WP7816T1) 8 R/W 0Ah
45.3.27/
1294
400E_B01C UART 7816 Wait N Register (UART5_WN7816) 8 R/W 00h
45.3.28/
1295
400E_B01D UART 7816 Wait FD Register (UART5_WF7816) 8 R/W 01h
45.3.29/
1295
400E_B01E UART 7816 Error Threshold Register (UART5_ET7816) 8 R/W 00h
45.3.30/
1296
400E_B01F UART 7816 Transmit Length Register (UART5_TL7816) 8 R/W 00h
45.3.31/
1297
45.3.1 UART Baud Rate Registers:High (UARTx_BDH)
This register, along with the BDL register, controls the prescale divisor for UART baud
rate generation. To update the 13-bit baud rate setting (SBR[12:0]), first write to BDH to
buffer the high half of the new value and then write to BDL. The working value in BDH
does not change until BDL is written.
BDL is reset to a non-zero value, but after reset the baud rate generator remains disabled
until the first time the receiver or transmitter is enabled (C2[RE] or C2[TE] bits are set).
Addresses: UART0_BDH is 4006_A000h base + 0h offset = 4006_A000h
UART1_BDH is 4006_B000h base + 0h offset = 4006_B000h
UART2_BDH is 4006_C000h base + 0h offset = 4006_C000h
UART3_BDH is 4006_D000h base + 0h offset = 4006_D000h
UART4_BDH is 400E_A000h base + 0h offset = 400E_A000h
UART5_BDH is 400E_B000h base + 0h offset = 400E_B000h
Bit 7 6 5 4 3 2 1 0
Read
LBKDIE RXEDGIE
0
SBR
Write
Reset
0 0 0 0 0 0 0 0
UARTx_BDH field descriptions
Field Description
7
LBKDIE
LIN Break Detect Interrupt Enable
LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt requests based on the state of
LBKDDMAS.
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1261