Information

UARTx_C1 field descriptions (continued)
Field Description
0 Selects internal loop back mode and receiver input is internally connected to transmitter output.
1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal.
4
M
9-bit or 8-bit Mode Select
This bit must be set when 7816E is set/enabled.
0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
3
WAKE
Receiver Wakeup Method Select
WAKE determines which condition wakes the UART: address mark in the most significant bit position of a
received data character or an idle condition on the receive pin input signal.
0 Idle-line wakeup.
1 Address-mark wakeup.
2
ILT
Idle Line Type Select
ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins
either after a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic
1s preceding the stop bit can cause false recognition of an idle character. Beginning the count after the
stop bit avoids false idle character recognition, but requires properly synchronized transmissions.
NOTE: In the case where UART is programmed with ILT = 1, a logic of 1'b0 is automatically shifted after
a received stop bit thus resetting the idle count.
NOTE: In the case where UART is programmed for IDLE line wakeup (RWU = 1 and WAKE = 0), ILT
has no effect on when the receiver starts counting logic 1s as idle character bits. In idle line
wakeup an idle character is recognized at anytime the receiver sees 10, 11, or 12 1s depending
on the M, PE, and C4[M10] bits.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position
immediately preceding the stop bit. This bit must be set when 7816E is set/enabled.
0 Parity function disabled.
1 Parity function enabled.
0
PT
Parity Type
PT determines whether the UART generates and checks for even parity or odd parity. With even parity,
an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an
odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.This bit must be
cleared when 7816E is set/enabled.
0 Even parity.
1 Odd parity.
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1264 Freescale Semiconductor, Inc.