Information

45.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Addresses: UART0_C2 is 4006_A000h base + 3h offset = 4006_A003h
UART1_C2 is 4006_B000h base + 3h offset = 4006_B003h
UART2_C2 is 4006_C000h base + 3h offset = 4006_C003h
UART3_C2 is 4006_D000h base + 3h offset = 4006_D003h
UART4_C2 is 400E_A000h base + 3h offset = 400E_A003h
UART5_C2 is 400E_B000h base + 3h offset = 400E_B003h
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C2 field descriptions
Field Description
7
TIE
Transmitter Interrupt or DMA Transfer Enable.
TIE enables the S1[TDRE] flag, to generate interrupt requests or DMA transfer requests, based on the
state of C5[TDMAS].
NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be
written outside of servicing of a DMA request.
0 TDRE interrupt and DMA transfer requests disabled.
1 TDRE interrupt or DMA transfer requests enabled.
6
TCIE
Transmission Complete Interrupt Enable
TCIE enables the transmission complete flag, S1[TC], to generate interrupt requests.
0 TC interrupt requests disabled.
1 TC interrupt requests enabled.
5
RIE
Receiver Full Interrupt or DMA Transfer Enable
RIE enables the S1[RDRF] flag, to generate interrupt requests or DMA transfer requests, based on the
state of C5[RDMAS].
0 RDRF interrupt and DMA transfer requests disabled.
1 RDRF interrupt or DMA transfer requests enabled
4
ILIE
Idle Line Interrupt Enable
ILIE enables the idle line flag, S1[IDLE], to generate interrupt requests, based on the state of
C5[ILDMAS].
0 IDLE interrupt requests disabled.
1 IDLE interrupt requests enabled.
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1265