Information
45.3.5 UART Status Register 1 (UARTx_S1)
The S1 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. This register can also be polled by the MCU to check the status of these bits. To
clear a flag, the status register should be read followed by a read or write (depending on
interrupt flag type) to the UART Data Register. Other instructions can be executed
between the two steps as long as it does not compromise the handling of I/O, but the
order of operations is important for flag clearing. When a flag is configured to trigger a
DMA request, assertion of the associated DMA done signal from the DMA controller,
clears the flag.
NOTE
If the condition that results in the assertion of the flag, interrupt
or DMA request is not resolved prior to clearing the flag, the
flag (and interrupt/DMA request) will reassert. For example, if
the DMA or interrupt service routine failed to write sufficient
data to the transmit buffer to raise it above the watermark level,
the flag will reassert and generate another interrupt or DMA
request.
NOTE
Reading an empty data register to clear one of these flags
causes the FIFO pointers to get out of alignment. A receive
FIFO flush reinitializes the pointers.
Addresses: UART0_S1 is 4006_A000h base + 4h offset = 4006_A004h
UART1_S1 is 4006_B000h base + 4h offset = 4006_B004h
UART2_S1 is 4006_C000h base + 4h offset = 4006_C004h
UART3_S1 is 4006_D000h base + 4h offset = 4006_D004h
UART4_S1 is 400E_A000h base + 4h offset = 400E_A004h
UART5_S1 is 400E_B000h base + 4h offset = 400E_B004h
Bit 7 6 5 4 3 2 1 0
Read TDRE TC RDRF IDLE OR NF FE PF
Write
Reset
1 1 0 0 0 0 0 0
UARTx_S1 field descriptions
Field Description
7
TDRE
Transmit Data Register Empty Flag
TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than
the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is
not included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1267