Information

45.3.6 UART Status Register 2 (UARTx_S2)
The S2 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. Also, this register can be polled by the MCU to check the status of these bits.
This register can be read or written at any time, with the exception of the MSBF and
RXINV bits which should only be changed by the user between transmit and receive
packets.
Addresses: UART0_S2 is 4006_A000h base + 5h offset = 4006_A005h
UART1_S2 is 4006_B000h base + 5h offset = 4006_B005h
UART2_S2 is 4006_C000h base + 5h offset = 4006_C005h
UART3_S2 is 4006_D000h base + 5h offset = 4006_D005h
UART4_S2 is 400E_A000h base + 5h offset = 400E_A005h
UART5_S2 is 400E_B000h base + 5h offset = 400E_B005h
Bit 7 6 5 4 3 2 1 0
Read
LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE
RAF
Write
Reset
0 0 0 0 0 0 0 0
UARTx_S2 field descriptions
Field Description
7
LBKDIF
LIN Break Detect Interrupt Flag
LBKDIF is set when LBKDE is set and a LIN break character is detected, when 11 consecutive logic 0s (if
C1[M] = 0) or 12 consecutive logic 0s (if C1[M] = 1) appear on the receiver input. LBKDIF is set right after
receiving the last LIN break character bit. LBKDIF is cleared by writing a 1 to it.
0 No LIN break character has been detected.
1 LIN break character has been detected.
6
RXEDGIF
RxD Pin Active Edge Interrupt Flag
RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs.
RXEDGIF is cleared by writing a 1 to it. See RXEDGIF description for additional details.
NOTE: The active edge is only detected when in two wire mode and on receive data coming from the
RxD pin.
0 No active edge on the receive pin has occurred.
1 An active edge on the receive pin has occurred.
5
MSBF
Most Significant Bit First
Setting this bit reverses the order of the bits that are transmitted and received on the wire. This bit does
not affect the polarity of the bits, the location of the parity bit or the location of the start or stop bits.This bit
is automatically set or cleared when C7816[INIT] and C7816[ISO7816E] are enabled and an initial
character is detected.
Table continues on the next page...
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1270 Freescale Semiconductor, Inc.