Information
UARTx_S2 field descriptions (continued)
Field Description
transfer actually takes 13 ETU with the 13th ETU slot being a inactive buffer. Hence in this
situation the RAF may deassert one ETU prior to actually being inactive.
0 UART receiver idle/inactive waiting for a start bit.
1 UART receiver active (RxD input not idle).
45.3.7 UART Control Register 3 (UARTx_C3)
Writing to R8 bit does not have any effect. The TXDIR and TXINV bits can only be
changed between transmit and receive packets.
Addresses: UART0_C3 is 4006_A000h base + 6h offset = 4006_A006h
UART1_C3 is 4006_B000h base + 6h offset = 4006_B006h
UART2_C3 is 4006_C000h base + 6h offset = 4006_C006h
UART3_C3 is 4006_D000h base + 6h offset = 4006_D006h
UART4_C3 is 400E_A000h base + 6h offset = 400E_A006h
UART5_C3 is 400E_B000h base + 6h offset = 400E_B006h
Bit 7 6 5 4 3 2 1 0
Read R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C3 field descriptions
Field Description
7
R8
Received Bit 8
R8 is the ninth data bit received when the UART is configured for 9-bit data format (C1[M] = 1) or
(C4[M10] = 1).
6
T8
Transmit Bit 8
T8 is the ninth data bit transmitted when the UART is configured for 9-bit data format (C1[M] = 1) or
(C4[M10] = 1).
NOTE: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.
The same value is transmitted until T8 is rewritten.
5
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
This bit determines whether the TXD pin is used as an input or output in the single-wire mode of
operation. This bit is relevant only to the single-wire mode. When C7816[ISO7816E] is set/enabled and
C7816[TTYPE] = 1, this bit is automatically cleared after the requested block has been transmitted. This
condition is detected when TL7816[TLEN] = 0 and 4 additional characters have been transmitted.
Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is being transmitted,
the hardware will automatically override this bit as needed. In this situation TXDIR will not reflect the
temporary state associated with the NACK.
Table continues on the next page...
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1272 Freescale Semiconductor, Inc.