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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 144 (13x13) 32-Bit 100 MHz I/O number 104

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UARTx_C3 field descriptions (continued)

Field Description

0 TXD pin is an input in single-wire mode.

1 TXD pin is an output in single-wire mode.

TXINV

Transmit Data Inversion.

Setting this bit reverses the polarity of the transmitted data output. In NRZ format, a one is represented by

a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In

IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a

one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining

idle high for a one for inverted polarity. This bit is automatically set or cleared when C7816[INIT] and

C7816[ISO7816E] are enabled and an initial character is detected.

NOTE: Setting TXINV inverts all transmitted values, including idle, break, start, and stop bits. In loop

mode, if TXINV is set, the receiver gets the transmit inversion bit when RXINV is disabled.When

C7816[ISO7816E] is set/enabled then only the transmitted data bits and parity bit are inverted.

0 Transmit data is not inverted.

1 Transmit data is inverted.

ORIE

Overrun Error Interrupt Enable

This bit enables the overrun error flag (S1[OR]) to generate interrupt requests.

0 OR interrupts are disabled.

1 OR interrupt requests are enabled.

NEIE

Noise Error Interrupt Enable

This bit enables the noise flag (S1[NF]) to generate interrupt requests.

0 NF interrupt requests are disabled.

1 NF interrupt requests are enabled.

FEIE

Framing Error Interrupt Enable

This bit enables the framing error flag (S1[FE]) to generate interrupt requests.

0 FE interrupt requests are disabled.

1 FE interrupt requests are enabled.

PEIE

Parity Error Interrupt Enable

This bit enables the parity error flag (S1[PF]) to generate interrupt requests.

0 PF interrupt requests are disabled.

1 PF interrupt requests are enabled.

45.3.8 UART Data Register (UARTx_D)

This register is actually two separate registers. Reads return the contents of the read-only

receive data register and writes go to the write-only transmit data register.

Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)

K10 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 1273