Information

45.3.9 UART Match Address Registers 1 (UARTx_MA1)
The MA1 and MA2 registers are compared to input data addresses when the most
significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the
following data is transferred to the data register. If a match fails, the following data is
discarded. These registers can be read and written at anytime.
Addresses: UART0_MA1 is 4006_A000h base + 8h offset = 4006_A008h
UART1_MA1 is 4006_B000h base + 8h offset = 4006_B008h
UART2_MA1 is 4006_C000h base + 8h offset = 4006_C008h
UART3_MA1 is 4006_D000h base + 8h offset = 4006_D008h
UART4_MA1 is 400E_A000h base + 8h offset = 400E_A008h
UART5_MA1 is 400E_B000h base + 8h offset = 400E_B008h
Bit 7 6 5 4 3 2 1 0
Read
MA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_MA1 field descriptions
Field Description
7–0
MA
Match Address
45.3.10 UART Match Address Registers 2 (UARTx_MA2)
These registers can be read and written at anytime. The MA1 and MA2 registers are
compared to input data addresses when the most significant bit is set and the associated
C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data
register. If a match fails, the following data is discarded.
Addresses: UART0_MA2 is 4006_A000h base + 9h offset = 4006_A009h
UART1_MA2 is 4006_B000h base + 9h offset = 4006_B009h
UART2_MA2 is 4006_C000h base + 9h offset = 4006_C009h
UART3_MA2 is 4006_D000h base + 9h offset = 4006_D009h
UART4_MA2 is 400E_A000h base + 9h offset = 400E_A009h
UART5_MA2 is 400E_B000h base + 9h offset = 400E_B009h
Bit 7 6 5 4 3 2 1 0
Read
MA
Write
Reset
0 0 0 0 0 0 0 0
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1275