Information
UARTx_MA2 field descriptions
Field Description
7–0
MA
Match Address
45.3.11 UART Control Register 4 (UARTx_C4)
Addresses: UART0_C4 is 4006_A000h base + Ah offset = 4006_A00Ah
UART1_C4 is 4006_B000h base + Ah offset = 4006_B00Ah
UART2_C4 is 4006_C000h base + Ah offset = 4006_C00Ah
UART3_C4 is 4006_D000h base + Ah offset = 4006_D00Ah
UART4_C4 is 400E_A000h base + Ah offset = 400E_A00Ah
UART5_C4 is 400E_B000h base + Ah offset = 400E_B00Ah
Bit 7 6 5 4 3 2 1 0
Read
MAEN1 MAEN2 M10 BRFA
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C4 field descriptions
Field Description
7
MAEN1
Match Address Mode Enable 1
Refer to Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN2 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA1 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when
C7816[ISO7816E] is set/enabled.
6
MAEN2
Match Address Mode Enable 2
Refer to Match address operation for more information.
0 All data received is transferred to the data buffer if MAEN1 is cleared.
1 All data received with the most significant bit cleared, is discarded. All data received with the most
significant bit set, is compared with contents of MA2 register. If no match occurs, the data is
discarded. If match occurs, data is transferred to the data buffer.This bit must be cleared when
C7816[ISO7816E] is set/enabled.
5
M10
10-bit Mode select
The M10 bit causes a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is
generated and interpreted as a parity bit. The M10 bit does not affect the LIN send or detect break
behavior. If M10 is set then both C1[M] and C1[PE] bits must also be set. This bit must be cleared when
C7816[ISO7816E] is set/enabled. Refer to Data format (non ISO-7816) for more information.
Table continues on the next page...
Memory map and registers
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
1276 Freescale Semiconductor, Inc.
