Information

UARTx_C4 field descriptions (continued)
Field Description
0 The parity bit is the ninth bit in the serial transmission.
1 The parity bit is the tenth bit in the serial transmission.
4–0
BRFA
Baud Rate Fine Adjust
This bit field is used to add more timing resolution to the average baud frequency, in increments of 1/32.
Refer to Baud rate generation for more information.
45.3.12 UART Control Register 5 (UARTx_C5)
Addresses: UART0_C5 is 4006_A000h base + Bh offset = 4006_A00Bh
UART1_C5 is 4006_B000h base + Bh offset = 4006_B00Bh
UART2_C5 is 4006_C000h base + Bh offset = 4006_C00Bh
UART3_C5 is 4006_D000h base + Bh offset = 4006_D00Bh
UART4_C5 is 400E_A000h base + Bh offset = 400E_A00Bh
UART5_C5 is 400E_B000h base + Bh offset = 400E_B00Bh
Bit 7 6 5 4 3 2 1 0
Read
TDMAS
0
RDMAS
0
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C5 field descriptions
Field Description
7
TDMAS
Transmitter DMA Select
TDMAS configures the transmit data register empty flag, S1[TDRE], to generate interrupt or DMA
requests if C2[TIE] is set.
NOTE: If C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not asserted when the
TDRE flag is set, regardless of the state of TDMAS.
NOTE: If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D register must not be
written outside of servicing of a DMA request.
0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request
interrupt service.
1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a
DMA transfer.
6
Reserved
This read-only field is reserved and always has the value zero.
5
RDMAS
Receiver Full DMA Select
RDMAS configures the receiver data register full flag, S1[RDRF], to generate interrupt or DMA requests if
C2[RIE] is set.
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1277